// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  hiddrphy_dx_static_reg_reg_offset_field.h
// Project line  :  IP
// Department    :  
// Author        :  Jason, Edward
// Version       :  .1
// Date          :  2011/11/29
// Description   :  The DDR PHY Controller Block
// Others        :  Generated automatically by nManager V4.2 
// History       :  Jason, Edward 2018/03/19 12:28:13 Create file
// ******************************************************************************

#ifndef __HIDDRPHY_DX_STATIC_REG_REG_OFFSET_FIELD_H__
#define __HIDDRPHY_DX_STATIC_REG_REG_OFFSET_FIELD_H__

#define HIDDRPHY_DX_STATIC_REG_DXCTL_TDC_OFFSET_CODE_H_LEN      5
#define HIDDRPHY_DX_STATIC_REG_DXCTL_TDC_OFFSET_CODE_H_OFFSET   17
#define HIDDRPHY_DX_STATIC_REG_DXCTL_TDC_OFFSET_CODE_V_LEN      5
#define HIDDRPHY_DX_STATIC_REG_DXCTL_TDC_OFFSET_CODE_V_OFFSET   12
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PLL_LT_LEN                 2
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PLL_LT_OFFSET              10
#define HIDDRPHY_DX_STATIC_REG_DXCTL_MARGIN_CAL_RANK0_EN_LEN    1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_MARGIN_CAL_RANK0_EN_OFFSET 9
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PLL_SP_LEN                 2
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PLL_SP_OFFSET              7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PLL_CPI_LEN                3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PLL_CPI_OFFSET             4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PLL_INIT_LEN               1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PLL_INIT_OFFSET            3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PLL_TESTEN_LEN             1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PLL_TESTEN_OFFSET          2

#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_ODTSEL_LEN        3
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_ODTSEL_OFFSET     29
#define HIDDRPHY_DX_STATIC_REG_DX_IOCTL_ODTSEL_LEN         3
#define HIDDRPHY_DX_STATIC_REG_DX_IOCTL_ODTSEL_OFFSET      26
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_PE_LEN          2
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_PE_OFFSET       6
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_HS_LEN          2
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_HS_OFFSET       4
#define HIDDRPHY_DX_STATIC_REG_TOP_IOCTL_ODT_OE_LEN        1
#define HIDDRPHY_DX_STATIC_REG_TOP_IOCTL_ODT_OE_OFFSET     2
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_DXIOPLDN_LEN    1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_DXIOPLDN_OFFSET 1

#define HIDDRPHY_DX_STATIC_REG_REG_DBG_BYT0_EVNTMT_DQ47_SEL_LEN    1
#define HIDDRPHY_DX_STATIC_REG_REG_DBG_BYT0_EVNTMT_DQ47_SEL_OFFSET 23
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DMSWAP_SEL_LEN                2
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DMSWAP_SEL_OFFSET             16
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSWAP_SEL_LEN                16
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSWAP_SEL_OFFSET             0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_RG_CK12P_LEN         4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RG_CK12P_OFFSET      20
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REGCM2_LEN           4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REGCM2_OFFSET        16
#define HIDDRPHY_DX_STATIC_REG_DXCTL_CK11P_DRAMCLK_LEN    4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_CK11P_DRAMCLK_OFFSET 12
#define HIDDRPHY_DX_STATIC_REG_DXCTL_CK10P_CMD2T_LEN      3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_CK10P_CMD2T_OFFSET   9
#define HIDDRPHY_DX_STATIC_REG_DXCTL_CK9P_CMD1T_LEN       5
#define HIDDRPHY_DX_STATIC_REG_DXCTL_CK9P_CMD1T_OFFSET    4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_CK0P_MCLK_LEN        4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_CK0P_MCLK_OFFSET     0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_PLL_LOCK_LEN    1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PLL_LOCK_OFFSET 31
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PLL_TEST_LEN    6
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PLL_TEST_OFFSET 0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_RX_PPFIFO_PTR_EN_LEN         1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RX_PPFIFO_PTR_EN_OFFSET      31
#define HIDDRPHY_DX_STATIC_REG_WFIFO_DXCTL_PASSTHROUGH_LEN        1
#define HIDDRPHY_DX_STATIC_REG_WFIFO_DXCTL_PASSTHROUGH_OFFSET     30
#define HIDDRPHY_DX_STATIC_REG_WFIFO_DXCTL_GCKEN_LEN              1
#define HIDDRPHY_DX_STATIC_REG_WFIFO_DXCTL_GCKEN_OFFSET           29
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_PHY_WDATA_RANKSW_LEN     3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_PHY_WDATA_RANKSW_OFFSET  26
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PPFIFO_PTR_EN_LEN            1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PPFIFO_PTR_EN_OFFSET         25
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RDFFSEL_2RANK_EN_LEN     1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RDFFSEL_2RANK_EN_OFFSET  24
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_WFIFO_MODE_LEN           1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_WFIFO_MODE_OFFSET        23
#define HIDDRPHY_DX_STATIC_REG_MARGIN_CAL_GATE_EN_LEN             1
#define HIDDRPHY_DX_STATIC_REG_MARGIN_CAL_GATE_EN_OFFSET          20
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_SEL_POS_RX_LEN           1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_SEL_POS_RX_OFFSET        19
#define HIDDRPHY_DX_STATIC_REG_PHY_TYPE_LEN                       2
#define HIDDRPHY_DX_STATIC_REG_PHY_TYPE_OFFSET                    17
#define HIDDRPHY_DX_STATIC_REG_LPDDR4_MODE_LEN                    1
#define HIDDRPHY_DX_STATIC_REG_LPDDR4_MODE_OFFSET                 16
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_EN_CMD_LEN              1
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_EN_CMD_OFFSET           15
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_SEL_CNT_CMD_LEN         1
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_SEL_CNT_CMD_OFFSET      14
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_SEL_REGREAD_CMD_LEN     1
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_SEL_REGREAD_CMD_OFFSET  13
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_TSTMODE_CMD_LEN         1
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_TSTMODE_CMD_OFFSET      12
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_EDIN_DQ47_SEL_LEN       3
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_EDIN_DQ47_SEL_OFFSET    9
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_EDIN_DQ03_SEL_LEN       3
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_EDIN_DQ03_SEL_OFFSET    6
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DVALID_SELFGEN_EN_LEN    1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DVALID_SELFGEN_EN_OFFSET 5
#define HIDDRPHY_DX_STATIC_REG_UT_MODE_LEN                        1
#define HIDDRPHY_DX_STATIC_REG_UT_MODE_OFFSET                     4
#define HIDDRPHY_DX_STATIC_REG_REG_HS_PHY_DEBUG_CK_DUTY_LEN       1
#define HIDDRPHY_DX_STATIC_REG_REG_HS_PHY_DEBUG_CK_DUTY_OFFSET    3

#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_ODT_IOPLDN_LEN         1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_ODT_IOPLDN_OFFSET      31
#define HIDDRPHY_DX_STATIC_REG_DXCTL_ODT_IOCTL_RONSEL_LEN         3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_ODT_IOCTL_RONSEL_OFFSET      28
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_SQUEACH_PD_LEN         2
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_SQUEACH_PD_OFFSET      24
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_GENVREF_PD_LEN         2
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_GENVREF_PD_OFFSET      12
#define HIDDRPHY_DX_STATIC_REG_DXCTL_ODT_IOCTL_RDSEL_N_LEN        3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_ODT_IOCTL_RDSEL_N_OFFSET     9
#define HIDDRPHY_DX_STATIC_REG_DXCTL_ODT_IOCTL_RDSEL_P_LEN        3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_ODT_IOCTL_RDSEL_P_OFFSET     6
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_GENVREF_RANGE_2_LEN    2
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_GENVREF_RANGE_2_OFFSET 0

#define HIDDRPHY_DX_STATIC_REG_IOCTL_DQ_RX_MODE1_LEN               1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DQ_RX_MODE1_OFFSET            31
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DQ_RX_MODE0_LEN               1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DQ_RX_MODE0_OFFSET            30
#define HIDDRPHY_DX_STATIC_REG_DQ_VREF_SEL0_LEN                    1
#define HIDDRPHY_DX_STATIC_REG_DQ_VREF_SEL0_OFFSET                 27
#define HIDDRPHY_DX_STATIC_REG_DQ_VREF_SEL1_LEN                    1
#define HIDDRPHY_DX_STATIC_REG_DQ_VREF_SEL1_OFFSET                 26
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_GENVREF_REFSEL_2_LEN    2
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_GENVREF_REFSEL_2_OFFSET 24
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_GENVREF_REFSEL_1_LEN    2
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_GENVREF_REFSEL_1_OFFSET 18
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_GENVREF_REFSEL_0_LEN    2
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_GENVREF_REFSEL_0_OFFSET 12
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_GENVREF_RANGE_1_LEN     2
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_GENVREF_RANGE_1_OFFSET  6
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_GENVREF_RANGE_0_LEN     2
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_GENVREF_RANGE_0_OFFSET  0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_PLL_LOCKIN_LEN          1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PLL_LOCKIN_OFFSET       16
#define HIDDRPHY_DX_STATIC_REG_DXCTL__PLL_FOPETESTREF_LEN    1
#define HIDDRPHY_DX_STATIC_REG_DXCTL__PLL_FOPETESTREF_OFFSET 14
#define HIDDRPHY_DX_STATIC_REG_DXCTL__PLL_FOPETESTFB_LEN     1
#define HIDDRPHY_DX_STATIC_REG_DXCTL__PLL_FOPETESTFB_OFFSET  12
#define HIDDRPHY_DX_STATIC_REG_DXCTL__PLL_LOCKT_SEL_LEN      1
#define HIDDRPHY_DX_STATIC_REG_DXCTL__PLL_LOCKT_SEL_OFFSET   10
#define HIDDRPHY_DX_STATIC_REG_DXCTL__PLL_INITSEL_LEN        1
#define HIDDRPHY_DX_STATIC_REG_DXCTL__PLL_INITSEL_OFFSET     8
#define HIDDRPHY_DX_STATIC_REG_DXCTL__PLL_EN_CAL_LEN         1
#define HIDDRPHY_DX_STATIC_REG_DXCTL__PLL_EN_CAL_OFFSET      6
#define HIDDRPHY_DX_STATIC_REG_DXCTL__PLL_ENPHSEL_LEN        1
#define HIDDRPHY_DX_STATIC_REG_DXCTL__PLL_ENPHSEL_OFFSET     4
#define HIDDRPHY_DX_STATIC_REG_DXCTL__PLL_BP_REFVCO_LEN      1
#define HIDDRPHY_DX_STATIC_REG_DXCTL__PLL_BP_REFVCO_OFFSET   2
#define HIDDRPHY_DX_STATIC_REG_DXCTL__PLL_BP_REFPFD_LEN      1
#define HIDDRPHY_DX_STATIC_REG_DXCTL__PLL_BP_REFPFD_OFFSET   0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_PHAZMETER_STATUS_LEN    16
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PHAZMETER_STATUS_OFFSET 16
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PHAZMETER_IN_LEN        16
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PHAZMETER_IN_OFFSET     0

#define HIDDRPHY_DX_STATIC_REG_DUMMY_IOCTL_RONSELP_LEN    3
#define HIDDRPHY_DX_STATIC_REG_DUMMY_IOCTL_RONSELP_OFFSET 29
#define HIDDRPHY_DX_STATIC_REG_DUMMY_IOCTL_RONSELN_LEN    3
#define HIDDRPHY_DX_STATIC_REG_DUMMY_IOCTL_RONSELN_OFFSET 26
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_RONBSELP_LEN     3
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_RONBSELP_OFFSET  23
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_RONBSELN_LEN     3
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_RONBSELN_OFFSET  20
#define HIDDRPHY_DX_STATIC_REG_DX_IOCTL_PRE_EM_LEN        2
#define HIDDRPHY_DX_STATIC_REG_DX_IOCTL_PRE_EM_OFFSET     18
#define HIDDRPHY_DX_STATIC_REG_DX_IOCTL_LP4X_EN_LEN       2
#define HIDDRPHY_DX_STATIC_REG_DX_IOCTL_LP4X_EN_OFFSET    16
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_PRE_EM_LEN       2
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_PRE_EM_OFFSET    14
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_LP4X_EN_LEN      2
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_LP4X_EN_OFFSET   12
#define HIDDRPHY_DX_STATIC_REG_DX_IOCTL_RONSELN_LEN       3
#define HIDDRPHY_DX_STATIC_REG_DX_IOCTL_RONSELN_OFFSET    9
#define HIDDRPHY_DX_STATIC_REG_DX_IOCTL_RONSELP_LEN       3
#define HIDDRPHY_DX_STATIC_REG_DX_IOCTL_RONSELP_OFFSET    6
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_RONSELN_LEN      3
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_RONSELN_OFFSET   3
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_RONSELP_LEN      3
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_RONSELP_OFFSET   0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_REFCLK_BDL_LEN    4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REFCLK_BDL_OFFSET 16
#define HIDDRPHY_DX_STATIC_REG_DXCTL_FBCLK_BDL_LEN     4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_FBCLK_BDL_OFFSET  0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQS_0_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQS_0_OFFSET 14
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DM_0_LEN     7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DM_0_OFFSET  7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DM_0_LEN     7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DM_0_OFFSET  0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQS_1_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQS_1_OFFSET 14
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DM_1_LEN     7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DM_1_OFFSET  7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DM_1_LEN     7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DM_1_OFFSET  0

#define HIDDRPHY_DX_STATIC_REG_REG_HS_PHY_DEBUG_DUTY_0_LEN              1
#define HIDDRPHY_DX_STATIC_REG_REG_HS_PHY_DEBUG_DUTY_0_OFFSET           31
#define HIDDRPHY_DX_STATIC_REG_REG_HS_PHY_DEBUG_0_LEN                   1
#define HIDDRPHY_DX_STATIC_REG_REG_HS_PHY_DEBUG_0_OFFSET                30
#define HIDDRPHY_DX_STATIC_REG_REG_SEL_DQSGATED_LA_2ND_DQS_0_LEN        1
#define HIDDRPHY_DX_STATIC_REG_REG_SEL_DQSGATED_LA_2ND_DQS_0_OFFSET     29
#define HIDDRPHY_DX_STATIC_REG_REG_RXMARGIN_INC_EN_DQS_0_LEN            1
#define HIDDRPHY_DX_STATIC_REG_REG_RXMARGIN_INC_EN_DQS_0_OFFSET         28
#define HIDDRPHY_DX_STATIC_REG_REG_RXMARGIN_DEC_EN_DQS_0_LEN            1
#define HIDDRPHY_DX_STATIC_REG_REG_RXMARGIN_DEC_EN_DQS_0_OFFSET         27
#define HIDDRPHY_DX_STATIC_REG_REG_RDQM_EN_DQS_0_LEN                    1
#define HIDDRPHY_DX_STATIC_REG_REG_RDQM_EN_DQS_0_OFFSET                 26
#define HIDDRPHY_DX_STATIC_REG_REG_MARGIN_2RANK_EN_DQS_0_LEN            1
#define HIDDRPHY_DX_STATIC_REG_REG_MARGIN_2RANK_EN_DQS_0_OFFSET         25
#define HIDDRPHY_DX_STATIC_REG_REG_WDQSBDL_2RANK_EN_DQS_0_LEN           1
#define HIDDRPHY_DX_STATIC_REG_REG_WDQSBDL_2RANK_EN_DQS_0_OFFSET        24
#define HIDDRPHY_DX_STATIC_REG_REG_TDVALID_VLE_DQS_0_LEN                1
#define HIDDRPHY_DX_STATIC_REG_REG_TDVALID_VLE_DQS_0_OFFSET             23
#define HIDDRPHY_DX_STATIC_REG_REG_TDVALID_MANCTL_DQS_0_LEN             1
#define HIDDRPHY_DX_STATIC_REG_REG_TDVALID_MANCTL_DQS_0_OFFSET          22
#define HIDDRPHY_DX_STATIC_REG_REG_WRANK_SRC_SEL_DQS_0_LEN              2
#define HIDDRPHY_DX_STATIC_REG_REG_WRANK_SRC_SEL_DQS_0_OFFSET           20
#define HIDDRPHY_DX_STATIC_REG_REG_GATEDERR_CHK_DIS_2ND_DQS_0_LEN       1
#define HIDDRPHY_DX_STATIC_REG_REG_GATEDERR_CHK_DIS_2ND_DQS_0_OFFSET    19
#define HIDDRPHY_DX_STATIC_REG_REG_GATEDLA_PASTHR_2ND_DQS_0_LEN         1
#define HIDDRPHY_DX_STATIC_REG_REG_GATEDLA_PASTHR_2ND_DQS_0_OFFSET      18
#define HIDDRPHY_DX_STATIC_REG_REG_TX_DQS_DCC_RANK1_DQS_0_LEN           7
#define HIDDRPHY_DX_STATIC_REG_REG_TX_DQS_DCC_RANK1_DQS_0_OFFSET        11
#define HIDDRPHY_DX_STATIC_REG_REG_LVDQSCLK_RANK1_SEL_DQS_0_LEN         1
#define HIDDRPHY_DX_STATIC_REG_REG_LVDQSCLK_RANK1_SEL_DQS_0_OFFSET      10
#define HIDDRPHY_DX_STATIC_REG_DXCTL_SYNC_PPFIFO_PTR_0_LEN              1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_SYNC_PPFIFO_PTR_0_OFFSET           9
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_SEL_REGREAD_DQ03_DQS_0_LEN    1
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_SEL_REGREAD_DQ03_DQS_0_OFFSET 8
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_SEL_REGREAD_DQ47_DQS_0_LEN    1
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_SEL_REGREAD_DQ47_DQS_0_OFFSET 7
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_REGREAD_DBGEN_DQS_0_LEN       1
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_REGREAD_DBGEN_DQS_0_OFFSET    6
#define HIDDRPHY_DX_STATIC_REG_REG_WDQSRANK0_PRE1T_SEL_DQS_0_LEN        1
#define HIDDRPHY_DX_STATIC_REG_REG_WDQSRANK0_PRE1T_SEL_DQS_0_OFFSET     5
#define HIDDRPHY_DX_STATIC_REG_REG_WDQSRANK1_PRE1T_SEL_DQS_0_LEN        1
#define HIDDRPHY_DX_STATIC_REG_REG_WDQSRANK1_PRE1T_SEL_DQS_0_OFFSET     4
#define HIDDRPHY_DX_STATIC_REG_REG_RX_TRANS_1RKEN_DQS_0_LEN             1
#define HIDDRPHY_DX_STATIC_REG_REG_RX_TRANS_1RKEN_DQS_0_OFFSET          3
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_EN_DQS_0_LEN                  1
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_EN_DQS_0_OFFSET               2
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_SEL_CNT_DQS_0_LEN             1
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_SEL_CNT_DQS_0_OFFSET          1
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_TSTMODE_DQS_0_LEN             1
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_TSTMODE_DQS_0_OFFSET          0

#define HIDDRPHY_DX_STATIC_REG_REG_HS_PHY_DEBUG_DUTY_1_LEN              1
#define HIDDRPHY_DX_STATIC_REG_REG_HS_PHY_DEBUG_DUTY_1_OFFSET           31
#define HIDDRPHY_DX_STATIC_REG_REG_HS_PHY_DEBUG_1_LEN                   1
#define HIDDRPHY_DX_STATIC_REG_REG_HS_PHY_DEBUG_1_OFFSET                30
#define HIDDRPHY_DX_STATIC_REG_REG_SEL_DQSGATED_LA_2ND_DQS_1_LEN        1
#define HIDDRPHY_DX_STATIC_REG_REG_SEL_DQSGATED_LA_2ND_DQS_1_OFFSET     29
#define HIDDRPHY_DX_STATIC_REG_REG_RXMARGIN_INC_EN_DQS_1_LEN            1
#define HIDDRPHY_DX_STATIC_REG_REG_RXMARGIN_INC_EN_DQS_1_OFFSET         28
#define HIDDRPHY_DX_STATIC_REG_REG_RXMARGIN_DEC_EN_DQS_1_LEN            1
#define HIDDRPHY_DX_STATIC_REG_REG_RXMARGIN_DEC_EN_DQS_1_OFFSET         27
#define HIDDRPHY_DX_STATIC_REG_REG_RDQM_EN_DQS_1_LEN                    1
#define HIDDRPHY_DX_STATIC_REG_REG_RDQM_EN_DQS_1_OFFSET                 26
#define HIDDRPHY_DX_STATIC_REG_REG_MARGIN_2RANK_EN_DQS_1_LEN            1
#define HIDDRPHY_DX_STATIC_REG_REG_MARGIN_2RANK_EN_DQS_1_OFFSET         25
#define HIDDRPHY_DX_STATIC_REG_REG_WDQSBDL_2RANK_EN_DQS_1_LEN           1
#define HIDDRPHY_DX_STATIC_REG_REG_WDQSBDL_2RANK_EN_DQS_1_OFFSET        24
#define HIDDRPHY_DX_STATIC_REG_REG_TDVALID_VLE_DQS_1_LEN                1
#define HIDDRPHY_DX_STATIC_REG_REG_TDVALID_VLE_DQS_1_OFFSET             23
#define HIDDRPHY_DX_STATIC_REG_REG_TDVALID_MANCTL_DQS_1_LEN             1
#define HIDDRPHY_DX_STATIC_REG_REG_TDVALID_MANCTL_DQS_1_OFFSET          22
#define HIDDRPHY_DX_STATIC_REG_REG_WRANK_SRC_SEL_DQS_1_LEN              2
#define HIDDRPHY_DX_STATIC_REG_REG_WRANK_SRC_SEL_DQS_1_OFFSET           20
#define HIDDRPHY_DX_STATIC_REG_REG_GATEDERR_CHK_DIS_2ND_DQS_1_LEN       1
#define HIDDRPHY_DX_STATIC_REG_REG_GATEDERR_CHK_DIS_2ND_DQS_1_OFFSET    19
#define HIDDRPHY_DX_STATIC_REG_REG_GATEDLA_PASTHR_2ND_DQS_1_LEN         1
#define HIDDRPHY_DX_STATIC_REG_REG_GATEDLA_PASTHR_2ND_DQS_1_OFFSET      18
#define HIDDRPHY_DX_STATIC_REG_REG_TX_DQS_DCC_RANK1_DQS_1_LEN           7
#define HIDDRPHY_DX_STATIC_REG_REG_TX_DQS_DCC_RANK1_DQS_1_OFFSET        11
#define HIDDRPHY_DX_STATIC_REG_REG_LVDQSCLK_RANK1_SEL_DQS_1_LEN         1
#define HIDDRPHY_DX_STATIC_REG_REG_LVDQSCLK_RANK1_SEL_DQS_1_OFFSET      10
#define HIDDRPHY_DX_STATIC_REG_DXCTL_SYNC_PPFIFO_PTR_1_LEN              1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_SYNC_PPFIFO_PTR_1_OFFSET           9
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_SEL_REGREAD_DQ03_DQS_1_LEN    1
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_SEL_REGREAD_DQ03_DQS_1_OFFSET 8
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_SEL_REGREAD_DQ47_DQS_1_LEN    1
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_SEL_REGREAD_DQ47_DQS_1_OFFSET 7
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_REGREAD_DBGEN_DQS_1_LEN       1
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_REGREAD_DBGEN_DQS_1_OFFSET    6
#define HIDDRPHY_DX_STATIC_REG_REG_WDQSRANK0_PRE1T_SEL_DQS_1_LEN        1
#define HIDDRPHY_DX_STATIC_REG_REG_WDQSRANK0_PRE1T_SEL_DQS_1_OFFSET     5
#define HIDDRPHY_DX_STATIC_REG_REG_WDQSRANK1_PRE1T_SEL_DQS_1_LEN        1
#define HIDDRPHY_DX_STATIC_REG_REG_WDQSRANK1_PRE1T_SEL_DQS_1_OFFSET     4
#define HIDDRPHY_DX_STATIC_REG_REG_RX_TRANS_1RKEN_DQS_1_LEN             1
#define HIDDRPHY_DX_STATIC_REG_REG_RX_TRANS_1RKEN_DQS_1_OFFSET          3
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_EN_DQS_1_LEN                  1
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_EN_DQS_1_OFFSET               2
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_SEL_CNT_DQS_1_LEN             1
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_SEL_CNT_DQS_1_OFFSET          1
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_TSTMODE_DQS_1_LEN             1
#define HIDDRPHY_DX_STATIC_REG_REG_EVNTMT_TSTMODE_DQS_1_OFFSET          0

#define HIDDRPHY_DX_STATIC_REG_REG_RESERVE_DQ0DTEN_DQS_0_LEN         1
#define HIDDRPHY_DX_STATIC_REG_REG_RESERVE_DQ0DTEN_DQS_0_OFFSET      31
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RXFIFO_R1T_SEL_DQS_0_LEN    1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RXFIFO_R1T_SEL_DQS_0_OFFSET 30
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DQSG_EXTEND_2T_DQS_0_LEN    1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DQSG_EXTEND_2T_DQS_0_OFFSET 29
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DQSG_EXTEND_EN_DQS_0_LEN    1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DQSG_EXTEND_EN_DQS_0_OFFSET 28
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DQSG_TOGGLE_EN_0_LEN        1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DQSG_TOGGLE_EN_0_OFFSET     27
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PTRGATED_EN_0_LEN               1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PTRGATED_EN_0_OFFSET            26
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_WPST_1P5TEN_0_LEN           1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_WPST_1P5TEN_0_OFFSET        25
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_SEL_LVDQSCLKDIV2_0_LEN      1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_SEL_LVDQSCLKDIV2_0_OFFSET   24
#define HIDDRPHY_DX_STATIC_REG_DXCTL_BUFPHYCLKDIV2_0_LEN             1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_BUFPHYCLKDIV2_0_OFFSET          23
#define HIDDRPHY_DX_STATIC_REG_DXCTL_LVDQCLKDIV2_0_LEN               1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_LVDQCLKDIV2_0_OFFSET            22
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSGATEDLA_0_LEN                1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSGATEDLA_0_OFFSET             21
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RXP_2ND_DM_0_LEN                1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RXP_2ND_DM_0_OFFSET             20
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RXN_2ND_DM_0_LEN                1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RXN_2ND_DM_0_OFFSET             19
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQS_H_0_LEN                     1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQS_H_0_OFFSET                  18
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQS_L_0_LEN                     1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQS_L_0_OFFSET                  17
#define HIDDRPHY_DX_STATIC_REG_REG_DQSDLY_PRI_EN_0_LEN               1
#define HIDDRPHY_DX_STATIC_REG_REG_DQSDLY_PRI_EN_0_OFFSET            16
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RXP_2ND_DQ_0_LEN                8
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RXP_2ND_DQ_0_OFFSET             8
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RXN_2ND_DQ_0_LEN                8
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RXN_2ND_DQ_0_OFFSET             0

#define HIDDRPHY_DX_STATIC_REG_REG_RESERVE_DQ0DTEN_DQS_1_LEN         1
#define HIDDRPHY_DX_STATIC_REG_REG_RESERVE_DQ0DTEN_DQS_1_OFFSET      31
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RXFIFO_R1T_SEL_DQS_1_LEN    1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RXFIFO_R1T_SEL_DQS_1_OFFSET 30
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DQSG_EXTEND_2T_DQS_1_LEN    1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DQSG_EXTEND_2T_DQS_1_OFFSET 29
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DQSG_EXTEND_EN_DQS_1_LEN    1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DQSG_EXTEND_EN_DQS_1_OFFSET 28
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DQSG_TOGGLE_EN_1_LEN        1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DQSG_TOGGLE_EN_1_OFFSET     27
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PTRGATED_EN_1_LEN               1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PTRGATED_EN_1_OFFSET            26
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_WPST_1P5TEN_1_LEN           1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_WPST_1P5TEN_1_OFFSET        25
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_SEL_LVDQSCLKDIV2_1_LEN      1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_SEL_LVDQSCLKDIV2_1_OFFSET   24
#define HIDDRPHY_DX_STATIC_REG_DXCTL_BUFPHYCLKDIV2_1_LEN             1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_BUFPHYCLKDIV2_1_OFFSET          23
#define HIDDRPHY_DX_STATIC_REG_DXCTL_LVDQCLKDIV2_1_LEN               1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_LVDQCLKDIV2_1_OFFSET            22
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSGATEDLA_1_LEN                1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSGATEDLA_1_OFFSET             21
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RXP_2ND_DM_1_LEN                1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RXP_2ND_DM_1_OFFSET             20
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RXN_2ND_DM_1_LEN                1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RXN_2ND_DM_1_OFFSET             19
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQS_H_1_LEN                     1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQS_H_1_OFFSET                  18
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQS_L_1_LEN                     1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQS_L_1_OFFSET                  17
#define HIDDRPHY_DX_STATIC_REG_REG_DQSDLY_PRI_EN_1_LEN               1
#define HIDDRPHY_DX_STATIC_REG_REG_DQSDLY_PRI_EN_1_OFFSET            16
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RXP_2ND_DQ_1_LEN                8
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RXP_2ND_DQ_1_OFFSET             8
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RXN_2ND_DQ_1_LEN                8
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RXN_2ND_DQ_1_OFFSET             0

#define HIDDRPHY_DX_STATIC_REG_DUMMY_IOCTL_RONBSELN_LEN     3
#define HIDDRPHY_DX_STATIC_REG_DUMMY_IOCTL_RONBSELN_OFFSET  27
#define HIDDRPHY_DX_STATIC_REG_DUMMY_IOCTL_RONBSELP_LEN     3
#define HIDDRPHY_DX_STATIC_REG_DUMMY_IOCTL_RONBSELP_OFFSET  24
#define HIDDRPHY_DX_STATIC_REG_DM_IOCTL_TX_DUTY_EN_LEN      2
#define HIDDRPHY_DX_STATIC_REG_DM_IOCTL_TX_DUTY_EN_OFFSET   22
#define HIDDRPHY_DX_STATIC_REG_DM_IOCTL_RX_DUTY_EN_LEN      2
#define HIDDRPHY_DX_STATIC_REG_DM_IOCTL_RX_DUTY_EN_OFFSET   20
#define HIDDRPHY_DX_STATIC_REG_DM_IOCTL_TX_DUTY_INC_LEN     2
#define HIDDRPHY_DX_STATIC_REG_DM_IOCTL_TX_DUTY_INC_OFFSET  18
#define HIDDRPHY_DX_STATIC_REG_DM_IOCTL_RX_DUTY_INC_LEN     2
#define HIDDRPHY_DX_STATIC_REG_DM_IOCTL_RX_DUTY_INC_OFFSET  16
#define HIDDRPHY_DX_STATIC_REG_DM_IOCTL_TX_DUTY_SEL_LEN     2
#define HIDDRPHY_DX_STATIC_REG_DM_IOCTL_TX_DUTY_SEL_OFFSET  14
#define HIDDRPHY_DX_STATIC_REG_DM_IOCTL_RX_DUTY_SEL_LEN     2
#define HIDDRPHY_DX_STATIC_REG_DM_IOCTL_RX_DUTY_SEL_OFFSET  12
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_TX_DUTY_EN_LEN     2
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_TX_DUTY_EN_OFFSET  10
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_RX_DUTY_EN_LEN     2
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_RX_DUTY_EN_OFFSET  8
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_TX_DUTY_INC_LEN    2
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_TX_DUTY_INC_OFFSET 6
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_RX_DUTY_INC_LEN    2
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_RX_DUTY_INC_OFFSET 4
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_TX_DUTY_SEL_LEN    2
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_TX_DUTY_SEL_OFFSET 2
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_RX_DUTY_SEL_LEN    2
#define HIDDRPHY_DX_STATIC_REG_DQS_IOCTL_RX_DUTY_SEL_OFFSET 0

#define HIDDRPHY_DX_STATIC_REG_REG_DQSOE_BY_IE_DQS_0_LEN      1
#define HIDDRPHY_DX_STATIC_REG_REG_DQSOE_BY_IE_DQS_0_OFFSET   31
#define HIDDRPHY_DX_STATIC_REG_REG_DQSOE_BY_WREN_DQS_0_LEN    1
#define HIDDRPHY_DX_STATIC_REG_REG_DQSOE_BY_WREN_DQS_0_OFFSET 30
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQCLK1X_0_LEN            3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQCLK1X_0_OFFSET         27
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQCLK2X_0_LEN            3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQCLK2X_0_OFFSET         24
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQCLK1X_RANK1_0_LEN      3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQCLK1X_RANK1_0_OFFSET   21
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQCLK2X_RANK1_0_LEN      3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQCLK2X_RANK1_0_OFFSET   18
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSGCLK1X_0_LEN          3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSGCLK1X_0_OFFSET       15
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSGCLK2X_0_LEN          3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSGCLK2X_0_OFFSET       12
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSCLK1X_0_LEN           3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSCLK1X_0_OFFSET        9
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSCLK2X_0_LEN           3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSCLK2X_0_OFFSET        6
#define HIDDRPHY_DX_STATIC_REG_DXCTL_MCLK1X_0_LEN             3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_MCLK1X_0_OFFSET          3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_MCLK2X_0_LEN             3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_MCLK2X_0_OFFSET          0

#define HIDDRPHY_DX_STATIC_REG_REG_DQSOE_BY_IE_DQS_1_LEN      1
#define HIDDRPHY_DX_STATIC_REG_REG_DQSOE_BY_IE_DQS_1_OFFSET   31
#define HIDDRPHY_DX_STATIC_REG_REG_DQSOE_BY_WREN_DQS_1_LEN    1
#define HIDDRPHY_DX_STATIC_REG_REG_DQSOE_BY_WREN_DQS_1_OFFSET 30
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQCLK1X_1_LEN            3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQCLK1X_1_OFFSET         27
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQCLK2X_1_LEN            3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQCLK2X_1_OFFSET         24
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQCLK1X_RANK1_1_LEN      3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQCLK1X_RANK1_1_OFFSET   21
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQCLK2X_RANK1_1_LEN      3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQCLK2X_RANK1_1_OFFSET   18
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSGCLK1X_1_LEN          3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSGCLK1X_1_OFFSET       15
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSGCLK2X_1_LEN          3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSGCLK2X_1_OFFSET       12
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSCLK1X_1_LEN           3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSCLK1X_1_OFFSET        9
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSCLK2X_1_LEN           3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSCLK2X_1_OFFSET        6
#define HIDDRPHY_DX_STATIC_REG_DXCTL_MCLK1X_1_LEN             3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_MCLK1X_1_OFFSET          3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_MCLK2X_1_LEN             3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_MCLK2X_1_OFFSET          0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_EVNTMT_RESULT_DQM2DQ7_BYT_0_LEN     1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_EVNTMT_RESULT_DQM2DQ7_BYT_0_OFFSET  27
#define HIDDRPHY_DX_STATIC_REG_DXCTL_EVNTMT_RESULT_DQS02DQ3_BYT_0_LEN    1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_EVNTMT_RESULT_DQS02DQ3_BYT_0_OFFSET 26
#define HIDDRPHY_DX_STATIC_REG_DXCTL_EVNTMT_DONE_DQM2DQ7_BYT_0_LEN       1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_EVNTMT_DONE_DQM2DQ7_BYT_0_OFFSET    25
#define HIDDRPHY_DX_STATIC_REG_DXCTL_EVNTMT_DONE_DQS02DQ3_BYT_0_LEN      1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_EVNTMT_DONE_DQS02DQ3_BYT_0_OFFSET   24
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RLRESULT_GDS_DQS_0_LEN              8
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RLRESULT_GDS_DQS_0_OFFSET           16
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_S0A_0_LEN                       1
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_S0A_0_OFFSET                    15
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_S0B_0_LEN                       1
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_S0B_0_OFFSET                    14
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_S1A_0_LEN                       1
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_S1A_0_OFFSET                    13
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_S1B_0_LEN                       1
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_S1B_0_OFFSET                    12
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_S2A_0_LEN                       1
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_S2A_0_OFFSET                    11
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_S2B_0_LEN                       1
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_S2B_0_OFFSET                    10
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_RDCNT_0_LEN                     4
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_RDCNT_0_OFFSET                  6
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_CA_0_LEN                        3
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_CA_0_OFFSET                     3
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_CB_0_LEN                        3
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_CB_0_OFFSET                     0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_EVNTMT_RESULT_DQM2DQ7_BYT_1_LEN     1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_EVNTMT_RESULT_DQM2DQ7_BYT_1_OFFSET  27
#define HIDDRPHY_DX_STATIC_REG_DXCTL_EVNTMT_RESULT_DQS02DQ3_BYT_1_LEN    1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_EVNTMT_RESULT_DQS02DQ3_BYT_1_OFFSET 26
#define HIDDRPHY_DX_STATIC_REG_DXCTL_EVNTMT_DONE_DQM2DQ7_BYT_1_LEN       1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_EVNTMT_DONE_DQM2DQ7_BYT_1_OFFSET    25
#define HIDDRPHY_DX_STATIC_REG_DXCTL_EVNTMT_DONE_DQS02DQ3_BYT_1_LEN      1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_EVNTMT_DONE_DQS02DQ3_BYT_1_OFFSET   24
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RLRESULT_GDS_DQS_1_LEN              8
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RLRESULT_GDS_DQS_1_OFFSET           16
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_S0A_1_LEN                       1
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_S0A_1_OFFSET                    15
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_S0B_1_LEN                       1
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_S0B_1_OFFSET                    14
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_S1A_1_LEN                       1
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_S1A_1_OFFSET                    13
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_S1B_1_LEN                       1
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_S1B_1_OFFSET                    12
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_S2A_1_LEN                       1
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_S2A_1_OFFSET                    11
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_S2B_1_LEN                       1
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_S2B_1_OFFSET                    10
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_RDCNT_1_LEN                     4
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_RDCNT_1_OFFSET                  6
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_CA_1_LEN                        3
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_CA_1_OFFSET                     3
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_CB_1_LEN                        3
#define HIDDRPHY_DX_STATIC_REG_DXDBG_DQS_CB_1_OFFSET                     0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_RSVDCTRL_0_LEN    16
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RSVDCTRL_0_OFFSET 0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_RSVDCTRL_1_LEN    16
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RSVDCTRL_1_OFFSET 0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSCLK1X_RANK1_0_LEN                3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSCLK1X_RANK1_0_OFFSET             29
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_POST_GATEDEN_0_LEN              1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_POST_GATEDEN_0_OFFSET           28
#define HIDDRPHY_DX_STATIC_REG_DXCTL_BYP_CLK_GATED_DIS_0_LEN             1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_BYP_CLK_GATED_DIS_0_OFFSET          27
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSCLK2X_RANK1_0_LEN                3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSCLK2X_RANK1_0_OFFSET             24
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_SEL_COMBOUT_0_LEN               1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_SEL_COMBOUT_0_OFFSET            23
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TSPC_SEL_0_LEN                  1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TSPC_SEL_0_OFFSET               22
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RESET_N_PHYUPDATE_REQ_0_LEN         1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RESET_N_PHYUPDATE_REQ_0_OFFSET      21
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_PN_DLYEN_0_LEN                  1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_PN_DLYEN_0_OFFSET               20
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_PRE_MARGIN_GATED_0_0_LEN        1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_PRE_MARGIN_GATED_0_0_OFFSET     19
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_PRE_MARGIN_GATED_1_0_LEN        1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_PRE_MARGIN_GATED_1_0_OFFSET     18
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_POST_MARGIN_GATED_0_0_LEN       1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_POST_MARGIN_GATED_0_0_OFFSET    17
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_POST_MARGIN_GATED_1_0_LEN       1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_POST_MARGIN_GATED_1_0_OFFSET    16
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DQSGDLY_DEMUX_GATED_0_0_LEN     1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DQSGDLY_DEMUX_GATED_0_0_OFFSET  15
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DQSDLY_DEMUX_GATED_1_0_LEN      1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DQSDLY_DEMUX_GATED_1_0_OFFSET   14
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_PHY_DQSG_STOP_ENABLE_0_LEN      1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_PHY_DQSG_STOP_ENABLE_0_OFFSET   13
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_PHY_DQSDLY_STOP_ENABLE_0_LEN    1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_PHY_DQSDLY_STOP_ENABLE_0_OFFSET 12
#define HIDDRPHY_DX_STATIC_REG_REG_RESETCON_GATED_EN_DQS_0_LEN           1
#define HIDDRPHY_DX_STATIC_REG_REG_RESETCON_GATED_EN_DQS_0_OFFSET        11
#define HIDDRPHY_DX_STATIC_REG_REG_OE_EXTEND1T_EN_0_LEN                  1
#define HIDDRPHY_DX_STATIC_REG_REG_OE_EXTEND1T_EN_0_OFFSET               10
#define HIDDRPHY_DX_STATIC_REG_REG_DQSG_TX_2PATH_0_LEN                   1
#define HIDDRPHY_DX_STATIC_REG_REG_DQSG_TX_2PATH_0_OFFSET                9
#define HIDDRPHY_DX_STATIC_REG_REG_SQUEACH_EN_0_LEN                      1
#define HIDDRPHY_DX_STATIC_REG_REG_SQUEACH_EN_0_OFFSET                   8
#define HIDDRPHY_DX_STATIC_REG_REG_DQSGLAT1T_EN_0_LEN                    1
#define HIDDRPHY_DX_STATIC_REG_REG_DQSGLAT1T_EN_0_OFFSET                 7
#define HIDDRPHY_DX_STATIC_REG_REG_SEL_HALFT_GATED_0_LEN                 1
#define HIDDRPHY_DX_STATIC_REG_REG_SEL_HALFT_GATED_0_OFFSET              6
#define HIDDRPHY_DX_STATIC_REG_REG_DYNAMIC_PUPDEN_0_LEN                  1
#define HIDDRPHY_DX_STATIC_REG_REG_DYNAMIC_PUPDEN_0_OFFSET               5
#define HIDDRPHY_DX_STATIC_REG_REG_DUMMYPAD_USE_0_LEN                    1
#define HIDDRPHY_DX_STATIC_REG_REG_DUMMYPAD_USE_0_OFFSET                 4
#define HIDDRPHY_DX_STATIC_REG_REG_ODTEN_GATED_0_LEN                     1
#define HIDDRPHY_DX_STATIC_REG_REG_ODTEN_GATED_0_OFFSET                  3
#define HIDDRPHY_DX_STATIC_REG_REG_GDS_R1T_SEL_0_LEN                     1
#define HIDDRPHY_DX_STATIC_REG_REG_GDS_R1T_SEL_0_OFFSET                  2
#define HIDDRPHY_DX_STATIC_REG_BUFRESETCONTN_GATED_TDC_0_LEN             1
#define HIDDRPHY_DX_STATIC_REG_BUFRESETCONTN_GATED_TDC_0_OFFSET          1
#define HIDDRPHY_DX_STATIC_REG_BUFRESETCONTN_GATED_DQSGERROR_0_LEN       1
#define HIDDRPHY_DX_STATIC_REG_BUFRESETCONTN_GATED_DQSGERROR_0_OFFSET    0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSCLK1X_RANK1_1_LEN                3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSCLK1X_RANK1_1_OFFSET             29
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_POST_GATEDEN_1_LEN              1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_POST_GATEDEN_1_OFFSET           28
#define HIDDRPHY_DX_STATIC_REG_DXCTL_BYP_CLK_GATED_DIS_1_LEN             1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_BYP_CLK_GATED_DIS_1_OFFSET          27
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSCLK2X_RANK1_1_LEN                3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSCLK2X_RANK1_1_OFFSET             24
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_SEL_COMBOUT_1_LEN               1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_SEL_COMBOUT_1_OFFSET            23
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TSPC_SEL_1_LEN                  1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TSPC_SEL_1_OFFSET               22
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RESET_N_PHYUPDATE_REQ_1_LEN         1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RESET_N_PHYUPDATE_REQ_1_OFFSET      21
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_PN_DLYEN_1_LEN                  1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_PN_DLYEN_1_OFFSET               20
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_PRE_MARGIN_GATED_0_1_LEN        1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_PRE_MARGIN_GATED_0_1_OFFSET     19
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_PRE_MARGIN_GATED_1_1_LEN        1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_PRE_MARGIN_GATED_1_1_OFFSET     18
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_POST_MARGIN_GATED_0_1_LEN       1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_POST_MARGIN_GATED_0_1_OFFSET    17
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_POST_MARGIN_GATED_1_1_LEN       1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_POST_MARGIN_GATED_1_1_OFFSET    16
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DQSGDLY_DEMUX_GATED_0_1_LEN     1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DQSGDLY_DEMUX_GATED_0_1_OFFSET  15
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DQSDLY_DEMUX_GATED_1_1_LEN      1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DQSDLY_DEMUX_GATED_1_1_OFFSET   14
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_PHY_DQSG_STOP_ENABLE_1_LEN      1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_PHY_DQSG_STOP_ENABLE_1_OFFSET   13
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_PHY_DQSDLY_STOP_ENABLE_1_LEN    1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_PHY_DQSDLY_STOP_ENABLE_1_OFFSET 12
#define HIDDRPHY_DX_STATIC_REG_REG_RESETCON_GATED_EN_DQS_1_LEN           1
#define HIDDRPHY_DX_STATIC_REG_REG_RESETCON_GATED_EN_DQS_1_OFFSET        11
#define HIDDRPHY_DX_STATIC_REG_REG_OE_EXTEND1T_EN_1_LEN                  1
#define HIDDRPHY_DX_STATIC_REG_REG_OE_EXTEND1T_EN_1_OFFSET               10
#define HIDDRPHY_DX_STATIC_REG_REG_DQSG_TX_2PATH_1_LEN                   1
#define HIDDRPHY_DX_STATIC_REG_REG_DQSG_TX_2PATH_1_OFFSET                9
#define HIDDRPHY_DX_STATIC_REG_REG_SQUEACH_EN_1_LEN                      1
#define HIDDRPHY_DX_STATIC_REG_REG_SQUEACH_EN_1_OFFSET                   8
#define HIDDRPHY_DX_STATIC_REG_REG_DQSGLAT1T_EN_1_LEN                    1
#define HIDDRPHY_DX_STATIC_REG_REG_DQSGLAT1T_EN_1_OFFSET                 7
#define HIDDRPHY_DX_STATIC_REG_REG_SEL_HALFT_GATED_1_LEN                 1
#define HIDDRPHY_DX_STATIC_REG_REG_SEL_HALFT_GATED_1_OFFSET              6
#define HIDDRPHY_DX_STATIC_REG_REG_DYNAMIC_PUPDEN_1_LEN                  1
#define HIDDRPHY_DX_STATIC_REG_REG_DYNAMIC_PUPDEN_1_OFFSET               5
#define HIDDRPHY_DX_STATIC_REG_REG_DUMMYPAD_USE_1_LEN                    1
#define HIDDRPHY_DX_STATIC_REG_REG_DUMMYPAD_USE_1_OFFSET                 4
#define HIDDRPHY_DX_STATIC_REG_REG_ODTEN_GATED_1_LEN                     1
#define HIDDRPHY_DX_STATIC_REG_REG_ODTEN_GATED_1_OFFSET                  3
#define HIDDRPHY_DX_STATIC_REG_REG_GDS_R1T_SEL_1_LEN                     1
#define HIDDRPHY_DX_STATIC_REG_REG_GDS_R1T_SEL_1_OFFSET                  2
#define HIDDRPHY_DX_STATIC_REG_BUFRESETCONTN_GATED_TDC_1_LEN             1
#define HIDDRPHY_DX_STATIC_REG_BUFRESETCONTN_GATED_TDC_1_OFFSET          1
#define HIDDRPHY_DX_STATIC_REG_BUFRESETCONTN_GATED_DQSGERROR_1_LEN       1
#define HIDDRPHY_DX_STATIC_REG_BUFRESETCONTN_GATED_DQSGERROR_1_OFFSET    0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DBG_GATED_N_0_LEN          1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DBG_GATED_N_0_OFFSET       10
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DBG_DQSDLY_ODTPAD_0_LEN    1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DBG_DQSDLY_ODTPAD_0_OFFSET 9
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DBG_FOTEST_0_LEN           1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DBG_FOTEST_0_OFFSET        8
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DESKEW_REGREAD_0_LEN           1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DESKEW_REGREAD_0_OFFSET        4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DBG_CONFIG_0_LEN               4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DBG_CONFIG_0_OFFSET            0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DBG_GATED_N_1_LEN          1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DBG_GATED_N_1_OFFSET       10
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DBG_DQSDLY_ODTPAD_1_LEN    1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DBG_DQSDLY_ODTPAD_1_OFFSET 9
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DBG_FOTEST_1_LEN           1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DBG_FOTEST_1_OFFSET        8
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DESKEW_REGREAD_1_LEN           1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DESKEW_REGREAD_1_OFFSET        4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DBG_CONFIG_1_LEN               4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DBG_CONFIG_1_OFFSET            0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_MCLK_DCC_0_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_MCLK_DCC_0_OFFSET 21
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQS_DCC_0_LEN     7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQS_DCC_0_OFFSET  14
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSG_DCC_0_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSG_DCC_0_OFFSET 7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQ_DCC_0_LEN      7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQ_DCC_0_OFFSET   0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_MCLK_DCC_1_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_MCLK_DCC_1_OFFSET 21
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQS_DCC_1_LEN     7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQS_DCC_1_OFFSET  14
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSG_DCC_1_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSG_DCC_1_OFFSET 7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQ_DCC_1_LEN      7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQ_DCC_1_OFFSET   0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSGCLK1X_RANK1_0_LEN      3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSGCLK1X_RANK1_0_OFFSET   28
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSGCLK2X_RANK1_0_LEN      3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSGCLK2X_RANK1_0_OFFSET   25
#define HIDDRPHY_DX_STATIC_REG_DXCTL_SW_MARGIN_CODE_0_LEN       5
#define HIDDRPHY_DX_STATIC_REG_DXCTL_SW_MARGIN_CODE_0_OFFSET    19
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSDLY_DEMUX_CODE_0_LEN    4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSDLY_DEMUX_CODE_0_OFFSET 8
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RXEXT_DLY_0_LEN            4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RXEXT_DLY_0_OFFSET         4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSG_EXTDLY_DQS_0_LEN      3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSG_EXTDLY_DQS_0_OFFSET   0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSGCLK1X_RANK1_1_LEN      3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSGCLK1X_RANK1_1_OFFSET   28
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSGCLK2X_RANK1_1_LEN      3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSGCLK2X_RANK1_1_OFFSET   25
#define HIDDRPHY_DX_STATIC_REG_DXCTL_SW_MARGIN_CODE_1_LEN       5
#define HIDDRPHY_DX_STATIC_REG_DXCTL_SW_MARGIN_CODE_1_OFFSET    19
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSDLY_DEMUX_CODE_1_LEN    4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSDLY_DEMUX_CODE_1_OFFSET 8
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RXEXT_DLY_1_LEN            4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_RXEXT_DLY_1_OFFSET         4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSG_EXTDLY_DQS_1_LEN      3
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSG_EXTDLY_DQS_1_OFFSET   0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DQSG_TOGGLE_CODE90_0_LEN     6
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DQSG_TOGGLE_CODE90_0_OFFSET  24
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_1RANK_ONLY_EN_DQS_0_LEN      1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_1RANK_ONLY_EN_DQS_0_OFFSET   20
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_CLKGATED_EN_DQS_0_LEN        1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_CLKGATED_EN_DQS_0_OFFSET     16
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PACK_CFG_RS_PASSTHROUGH_0_LEN    1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PACK_CFG_RS_PASSTHROUGH_0_OFFSET 12
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_ASY_CMD_DECODE_SEL_0_LEN     1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_ASY_CMD_DECODE_SEL_0_OFFSET  8
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RST_N_0_LEN                  1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RST_N_0_OFFSET               6
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DBGMODE_BYT1_SEL_0_LEN       1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DBGMODE_BYT1_SEL_0_OFFSET    4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_CLKGATED_DIS_0_LEN           4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_CLKGATED_DIS_0_OFFSET        0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DQSG_TOGGLE_CODE90_1_LEN     6
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DQSG_TOGGLE_CODE90_1_OFFSET  24
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_1RANK_ONLY_EN_DQS_1_LEN      1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_1RANK_ONLY_EN_DQS_1_OFFSET   20
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_CLKGATED_EN_DQS_1_LEN        1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_CLKGATED_EN_DQS_1_OFFSET     16
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PACK_CFG_RS_PASSTHROUGH_1_LEN    1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_PACK_CFG_RS_PASSTHROUGH_1_OFFSET 12
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_ASY_CMD_DECODE_SEL_1_LEN     1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_ASY_CMD_DECODE_SEL_1_OFFSET  8
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RST_N_1_LEN                  1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RST_N_1_OFFSET               6
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DBGMODE_BYT1_SEL_1_LEN       1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DBGMODE_BYT1_SEL_1_OFFSET    4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_CLKGATED_DIS_1_LEN           4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_CLKGATED_DIS_1_OFFSET        0

#define HIDDRPHY_DX_STATIC_REG_IOCTL_DUMMY_SQUEACH_PD_0_LEN       1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DUMMY_SQUEACH_PD_0_OFFSET    16
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DUMMY_SQUEACH_CLR_B_0_LEN    1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DUMMY_SQUEACH_CLR_B_0_OFFSET 15
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DIFFDUMMY_EN_0_LEN           1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DIFFDUMMY_EN_0_OFFSET        14
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DUMMY_PULLDN_0_LEN           1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DUMMY_PULLDN_0_OFFSET        13
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DUMMY_OE_0_LEN               1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DUMMY_OE_0_OFFSET            12
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_DIFFDQS_EN_0_LEN       1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_DIFFDQS_EN_0_OFFSET    11
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DXIOPLDN_DM_0_LEN            1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DXIOPLDN_DM_0_OFFSET         7
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DXIOPLDN_DQ_0_LEN            1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DXIOPLDN_DQ_0_OFFSET         6
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DUMMY_RX_MODE1_0_LEN         1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DUMMY_RX_MODE1_0_OFFSET      5
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DUMMY_RX_MODE0_0_LEN         1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DUMMY_RX_MODE0_0_OFFSET      4
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DM_RX_MODE1_0_LEN            1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DM_RX_MODE1_0_OFFSET         3
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DM_RX_MODE0_0_LEN            1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DM_RX_MODE0_0_OFFSET         2
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DQS_RX_MODE1_0_LEN           1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DQS_RX_MODE1_0_OFFSET        1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DQS_RX_MODE0_0_LEN           1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DQS_RX_MODE0_0_OFFSET        0

#define HIDDRPHY_DX_STATIC_REG_IOCTL_DUMMY_SQUEACH_PD_1_LEN       1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DUMMY_SQUEACH_PD_1_OFFSET    16
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DUMMY_SQUEACH_CLR_B_1_LEN    1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DUMMY_SQUEACH_CLR_B_1_OFFSET 15
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DIFFDUMMY_EN_1_LEN           1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DIFFDUMMY_EN_1_OFFSET        14
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DUMMY_PULLDN_1_LEN           1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DUMMY_PULLDN_1_OFFSET        13
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DUMMY_OE_1_LEN               1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DUMMY_OE_1_OFFSET            12
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_DIFFDQS_EN_1_LEN       1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_IOCTL_DIFFDQS_EN_1_OFFSET    11
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DXIOPLDN_DM_1_LEN            1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DXIOPLDN_DM_1_OFFSET         7
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DXIOPLDN_DQ_1_LEN            1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DXIOPLDN_DQ_1_OFFSET         6
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DUMMY_RX_MODE1_1_LEN         1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DUMMY_RX_MODE1_1_OFFSET      5
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DUMMY_RX_MODE0_1_LEN         1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DUMMY_RX_MODE0_1_OFFSET      4
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DM_RX_MODE1_1_LEN            1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DM_RX_MODE1_1_OFFSET         3
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DM_RX_MODE0_1_LEN            1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DM_RX_MODE0_1_OFFSET         2
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DQS_RX_MODE1_1_LEN           1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DQS_RX_MODE1_1_OFFSET        1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DQS_RX_MODE0_1_LEN           1
#define HIDDRPHY_DX_STATIC_REG_IOCTL_DQS_RX_MODE0_1_OFFSET        0

#define HIDDRPHY_DX_STATIC_REG_DX_IOCTL_TX_DUTY_EN_LEN    16
#define HIDDRPHY_DX_STATIC_REG_DX_IOCTL_TX_DUTY_EN_OFFSET 16
#define HIDDRPHY_DX_STATIC_REG_DX_IOCTL_RX_DUTY_EN_LEN    16
#define HIDDRPHY_DX_STATIC_REG_DX_IOCTL_RX_DUTY_EN_OFFSET 0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ3_0_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ3_0_OFFSET 21
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ2_0_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ2_0_OFFSET 14
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ1_0_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ1_0_OFFSET 7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ0_0_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ0_0_OFFSET 0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ3_1_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ3_1_OFFSET 21
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ2_1_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ2_1_OFFSET 14
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ1_1_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ1_1_OFFSET 7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ0_1_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ0_1_OFFSET 0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ7_0_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ7_0_OFFSET 21
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ6_0_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ6_0_OFFSET 14
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ5_0_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ5_0_OFFSET 7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ4_0_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ4_0_OFFSET 0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ7_1_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ7_1_OFFSET 21
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ6_1_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ6_1_OFFSET 14
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ5_1_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ5_1_OFFSET 7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ4_1_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RX_DCC_DQ4_1_OFFSET 0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ3_0_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ3_0_OFFSET 21
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ2_0_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ2_0_OFFSET 14
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ1_0_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ1_0_OFFSET 7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ0_0_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ0_0_OFFSET 0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ3_1_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ3_1_OFFSET 21
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ2_1_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ2_1_OFFSET 14
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ1_1_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ1_1_OFFSET 7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ0_1_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ0_1_OFFSET 0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ7_0_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ7_0_OFFSET 21
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ6_0_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ6_0_OFFSET 14
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ5_0_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ5_0_OFFSET 7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ4_0_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ4_0_OFFSET 0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ7_1_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ7_1_OFFSET 21
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ6_1_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ6_1_OFFSET 14
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ5_1_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ5_1_OFFSET 7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ4_1_LEN    7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_TX_DCC_DQ4_1_OFFSET 0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSG_CODE_AFT_0_LEN             4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSG_CODE_AFT_0_OFFSET          20
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSG_CODE_BEF_0_LEN             4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSG_CODE_BEF_0_OFFSET          16
#define HIDDRPHY_DX_STATIC_REG_DXCTL_BYP_CK90_DATA_CODE_DQS_0_LEN    10
#define HIDDRPHY_DX_STATIC_REG_DXCTL_BYP_CK90_DATA_CODE_DQS_0_OFFSET 0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSG_CODE_AFT_1_LEN             4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSG_CODE_AFT_1_OFFSET          20
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSG_CODE_BEF_1_LEN             4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DQSG_CODE_BEF_1_OFFSET          16
#define HIDDRPHY_DX_STATIC_REG_DXCTL_BYP_CK90_DATA_CODE_DQS_1_LEN    10
#define HIDDRPHY_DX_STATIC_REG_DXCTL_BYP_CK90_DATA_CODE_DQS_1_OFFSET 0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_BYP_CK90_TO_PHY_0_LEN    10
#define HIDDRPHY_DX_STATIC_REG_DXCTL_BYP_CK90_TO_PHY_0_OFFSET 16

#define HIDDRPHY_DX_STATIC_REG_DXCTL_BYP_CK90_TO_PHY_1_LEN    10
#define HIDDRPHY_DX_STATIC_REG_DXCTL_BYP_CK90_TO_PHY_1_OFFSET 16

#define HIDDRPHY_DX_STATIC_REG_DX_IOCTL_TX_DUTY_INC_LEN    16
#define HIDDRPHY_DX_STATIC_REG_DX_IOCTL_TX_DUTY_INC_OFFSET 16
#define HIDDRPHY_DX_STATIC_REG_DX_IOCTL_RX_DUTY_INC_LEN    16
#define HIDDRPHY_DX_STATIC_REG_DX_IOCTL_RX_DUTY_INC_OFFSET 0

#define HIDDRPHY_DX_STATIC_REG_DX_IOCTL_TX_DUTY_SEL_LEN    16
#define HIDDRPHY_DX_STATIC_REG_DX_IOCTL_TX_DUTY_SEL_OFFSET 16
#define HIDDRPHY_DX_STATIC_REG_DX_IOCTL_RX_DUTY_SEL_LEN    16
#define HIDDRPHY_DX_STATIC_REG_DX_IOCTL_RX_DUTY_SEL_OFFSET 0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_MARGIN_MIN_LIMIT_LEN     5
#define HIDDRPHY_DX_STATIC_REG_DXCTL_MARGIN_MIN_LIMIT_OFFSET  17
#define HIDDRPHY_DX_STATIC_REG_DXCTL_MARGIN_MAX_LIMIT_LEN     5
#define HIDDRPHY_DX_STATIC_REG_DXCTL_MARGIN_MAX_LIMIT_OFFSET  12
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DEC_MARGIN_TAP_LEN       2
#define HIDDRPHY_DX_STATIC_REG_DXCTL_DEC_MARGIN_TAP_OFFSET    10
#define HIDDRPHY_DX_STATIC_REG_DXCTL_INC_MARGIN_TAP_LEN       2
#define HIDDRPHY_DX_STATIC_REG_DXCTL_INC_MARGIN_TAP_OFFSET    8
#define HIDDRPHY_DX_STATIC_REG_DX_HALF_PHASE_SEL_LEN          1
#define HIDDRPHY_DX_STATIC_REG_DX_HALF_PHASE_SEL_OFFSET       1
#define HIDDRPHY_DX_STATIC_REG_DX_HALF_PHASE_SEL_RANK1_LEN    1
#define HIDDRPHY_DX_STATIC_REG_DX_HALF_PHASE_SEL_RANK1_OFFSET 0

#define HIDDRPHY_DX_STATIC_REG_REG_RESERVE_3RD_LEN    32
#define HIDDRPHY_DX_STATIC_REG_REG_RESERVE_3RD_OFFSET 0

#define HIDDRPHY_DX_STATIC_REG_DUMMY_IOCTL_TX_DUTY_EN_LEN     2
#define HIDDRPHY_DX_STATIC_REG_DUMMY_IOCTL_TX_DUTY_EN_OFFSET  10
#define HIDDRPHY_DX_STATIC_REG_DUMMY_IOCTL_TX_DUTY_INC_LEN    2
#define HIDDRPHY_DX_STATIC_REG_DUMMY_IOCTL_TX_DUTY_INC_OFFSET 8
#define HIDDRPHY_DX_STATIC_REG_DUMMY_IOCTL_TX_DUTY_SEL_LEN    2
#define HIDDRPHY_DX_STATIC_REG_DUMMY_IOCTL_TX_DUTY_SEL_OFFSET 6
#define HIDDRPHY_DX_STATIC_REG_DUMMY_IOCTL_RX_DUTY_EN_LEN     2
#define HIDDRPHY_DX_STATIC_REG_DUMMY_IOCTL_RX_DUTY_EN_OFFSET  4
#define HIDDRPHY_DX_STATIC_REG_DUMMY_IOCTL_RX_DUTY_INC_LEN    2
#define HIDDRPHY_DX_STATIC_REG_DUMMY_IOCTL_RX_DUTY_INC_OFFSET 2
#define HIDDRPHY_DX_STATIC_REG_DUMMY_IOCTL_RX_DUTY_SEL_LEN    2
#define HIDDRPHY_DX_STATIC_REG_DUMMY_IOCTL_RX_DUTY_SEL_OFFSET 0

#define HIDDRPHY_DX_STATIC_REG_DXCTL_MARGIN_CODE_LEN                    5
#define HIDDRPHY_DX_STATIC_REG_DXCTL_MARGIN_CODE_OFFSET                 26
#define HIDDRPHY_DX_STATIC_REG_DXCTL_MARGIN_TRACK_CLR_LEN               1
#define HIDDRPHY_DX_STATIC_REG_DXCTL_MARGIN_TRACK_CLR_OFFSET            25
#define HIDDRPHY_DX_STATIC_REG_DXCTL_MARGIN_DBG_CODE_LEN                9
#define HIDDRPHY_DX_STATIC_REG_DXCTL_MARGIN_DBG_CODE_OFFSET             16
#define HIDDRPHY_DX_STATIC_REG_DXCTL_MARGIN_DBG_SEL_LEN                 7
#define HIDDRPHY_DX_STATIC_REG_DXCTL_MARGIN_DBG_SEL_OFFSET              9
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DBGMODE_SEL_LEN                5
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_DBGMODE_SEL_OFFSET             4
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RDVREF_RANKSEL_EN_DQS_LEN      2
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RDVREF_RANKSEL_EN_DQS_OFFSET   2
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RDVREF_RANKSEL_MODE_DQS_LEN    2
#define HIDDRPHY_DX_STATIC_REG_DXCTL_REG_RDVREF_RANKSEL_MODE_DQS_OFFSET 0

#define HIDDRPHY_DX_STATIC_REG_DXRSVDREG1_LEN    32
#define HIDDRPHY_DX_STATIC_REG_DXRSVDREG1_OFFSET 0

#define HIDDRPHY_DX_STATIC_REG_DXRSVDREG2_LEN    32
#define HIDDRPHY_DX_STATIC_REG_DXRSVDREG2_OFFSET 0

#endif // __HIDDRPHY_DX_STATIC_REG_REG_OFFSET_FIELD_H__
